1. Field of the Invention
The invention relates to a method for manufacturing a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device.
2. Background Art
Nonvolatile semiconductor memory devices of flash memory and the like conventionally are constructed by two-dimensionally integrating elements on the surface of a silicon substrate. To increase the storage capacity of such flash memory, it is necessary to downscale by reducing the dimensions of the individual elements. However, such downscaling in recent years has become difficult in regard to both cost and technology.
Many methods of three-dimensionally integrating elements have been proposed to solve such problems. In particular, a collectively patterned three-dimensional stacked memory having high productivity is considered to be promising (refer to JP-A 2007-266143 (Kokai)).
In such technology, a stacked unit is formed by alternately stacking electrode films and insulating films on a silicon substrate. Subsequently, through-holes are made in the stacked unit by collective patterning. A charge storage layer is formed on a side face of each through-hole, and silicon is filled into the interior of the through-hole to form a silicon pillar. A memory cell is thereby formed at an intersection between each electrode film and the silicon pillar. The end portions of the stacked unit are patterned into a stairstep configuration; an inter-layer insulating film is provided up onto the end portions of the stairstep configuration around the stacked unit; and contacts are buried in the inter-layer insulating film to connect to the end portions of each of the electrode films. Multiple metal interconnects are laid above the inter-layer insulating film and connected to the end portions of each of the electrode films via the contacts. Thereby, the potential of each of the electrode films can be controlled mutually independently via the metal interconnects and the contacts.
In such a collectively patterned three-dimensional stacked memory, a charge can be removed from and put into the charge storage layer from the silicon pillar to store information by controlling an electrical potential of each of the electrode films and each of the silicon pillars. According to such technology, the chip surface area per bit can be reduced and costs can be reduced by stacking multiple electrode films on the silicon substrate. Also, the three dimensional stacked memory can be formed by collectively patterning the stacked unit. Therefore, the number of lithography processes does not increase and cost increases can be suppressed even in the case where the number of stacks increases.
Thus, one feature of collectively patterned three-dimensional stacked memory is the ability to simultaneously realize a capacity increase and a bit cost reduction by increasing the number of stacks. However, in the case where the capacity is increased simply by increasing the number of film formations of the stacked films, the number of film formation processes for the stacked films and the time necessary for such processes gradually reaches a level that cannot be ignored.
Moreover, regarding the aspect of production equipment, the method of simply increasing the number of film formations results in a higher burden on the film formation apparatuses;
and the balance of the number of apparatuses by apparatus type becomes quite different from that of other semiconductor products. Such a result may cause great losses to occur in the case where production equipment must be converted to other products according to market needs.
Therefore, a method and a structure thereof are desired to realize the collectively patterned three dimensional stacked memory recited above by fewer film formation processes even in the case where the number of stacks increases.